AttentionCap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction

A new Transformer-based model called AttentionCap aims to improve the accuracy of full-chip capacitance extraction, a critical step in electronic design automation, according to research published on arXiv [1]. The model addresses limitations in existing deep-learning approaches that are tied to specific process nodes [1]. Rule-based pattern matching for capacitance extraction is becoming difficult to sustain at advanced semiconductor nodes, driving interest in deep-learning alternatives [1]. Current methods using multi-layer perceptrons (MLPs) and convolutional neural networks (CNNs) constrain their input to fixed metal-layer combinations within a single process node, which limits their practical use [1]. The researchers behind AttentionCap identified a structural similarity between the capacitance matrix and the attention mechanism that underpins Transformer architectures [1]. They designed the model with a Gram representation framework, a physics-aligned symmetric-attention output layer, and a normalized Laplacian loss function [1]. A process-node embedding was also introduced to enable multi-node learning [1]. Trained on synthetic data, AttentionCap achieved a 0.67% self-capacitance error and a 3.99% coupling-capacitance error when tested on unseen real designs in a multi-layer and multi-node setting [1]. Compared to a CNN-Cap baseline, the model delivered 4.6 times lower self-capacitance error, 5.7 times lower coupling-capacitance error, and a 192-fold increase in inference speed [1]. The work further demonstrated that a pretrained AttentionCap can transfer to an unseen process node using only 5,000 samples and 4,000 fine-tuning steps [1]. The code and data for the project have been made publicly available on GitHub [1].