BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models

A new surrogate model called BigPower can estimate fine-grained, module-level power consumption in CPUs directly from source-level design information, according to research submitted to arXiv in June 2026 [1]. The approach uses large language model-based representations to bypass conventional simulation-based workflows [2]. The work, titled "BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models," was posted on the arXiv preprint server on 11 June 2026 [1]. The authors describe a hierarchical model that incorporates architectural hierarchy, module connectivity, configuration parameters, and workload context to produce power estimates without requiring additional simulation during inference [2]. Experimental validation was conducted on the open-source XiangShan processor family, demonstrating practical fine-grained power estimation across diverse configurations and workloads [2]. The paper appears at a time when energy consumption in computing infrastructure is under increasing scrutiny. Global data center electricity consumption was estimated at around 415 terawatt hours in 2024, roughly 1.5 percent of global electricity demand, and the International Energy Agency projects that figure could double by 2030 [3]. Hyperscale and colocation facilities now account for approximately 74 percent of U.S. server energy consumption, a share that has grown significantly over the past decade as workloads migrate away from on-premises enterprise infrastructure [3]. BigPower's source-level approach represents a departure from traditional power estimation methods that rely on simulation-derived information or post-silicon analysis [2]. Large language models, which are trained with self-supervised learning on vast amounts of text, have been adapted for a range of tasks beyond natural language generation [11]. By applying LLM-based representations to hardware design artifacts, the researchers aim to give chip architects earlier and more accessible power feedback during the design cycle. The research was disseminated through arXiv, an open-access repository of electronic preprints that has been operating since August 1991 and now receives about 24,000 submissions per month as of November 2024 [9]. The paper's abstract page includes integration with arXivLabs, a framework launched in 2020 that allows community collaborators to develop experimental tools such as citation explorers and code finders directly on the site [7][8].