EstRTL: Functional Estimation Guided RTL Code Generation

A new framework called EstRTL aims to improve the functional correctness of AI-generated hardware description code, addressing a persistent weakness in current large language model approaches to chip design [1]. The framework, detailed in a paper submitted to arXiv on 1 June, introduces a three-stage paradigm: Generation, Estimation, and Correction [1]. A functional estimation agent statically evaluates the generated register transfer level (RTL) code, assigning a quantitative score and producing a human-readable requirements comparison. Based on this assessment, the agent decides whether to output the code directly, return it for regeneration, or forward it to a code correction agent [2]. RTL code describes the flow of data between hardware registers and the logical operations performed on that data, making its correctness essential for functional chip design. The authors note that while LLMs have been applied to automate RTL generation, existing methods often emphasize model fine-tuning and expansion techniques without sufficient focus on whether the output behaves as intended in real hardware [2]. The EstRTL framework is designed to be model-agnostic and can be applied to various LLMs built for RTL code generation [1]. In experiments, the system improved the correctness of RTL code produced by a generic LLM by 3.2% to 9.0% [2]. The researchers have open-sourced the code and experimental results on an anonymous repository linked in the paper [1]. The work arrives as the semiconductor industry continues to explore AI-assisted design flows to manage escalating chip complexity. The paper’s emphasis on static functional score estimation provides a layer of transparency that the authors argue is often missing from purely generative approaches [2].