Future Transistor Stacking Plans Start to Diverge

The semiconductor industry is coalescing around a new transistor architecture that stacks two devices vertically, a shift expected to halve circuit footprints. IBM detailed its sequential approach, called Nanostack, at the IEEE VLSI Symposium, projecting significant performance and efficiency gains over current 2-nanometer-node chips [1]. The device, known in research as the complementary field-effect transistor (CFET), stacks p-channel and n-channel nanosheet transistors instead of placing them side by side [1]. While Intel, Samsung, and TSMC are pursuing a monolithic process that builds both devices simultaneously, IBM is advancing a sequential method that constructs one complete layer of transistors before adding the next [1]. IBM's plans also call for the transistor pair to be slightly staggered, a design the company says allows independent front-side and backside contacts for each transistor [1]. IBM claims its Nanostack technology will deliver as much as a 50 percent performance boost, a 70 percent efficiency improvement, and a 40 percent shrink of a computer chip's memory compared to today's 2-nanometer-node chips [1]. Huiming Bu, IBM Semiconductors vice president of global R&D, described the platform's potential. "It is a new transistor platform that enables so many innovations to come," Bu said [1]. A central challenge for sequential CFETs is thermal management. The lower transistor tiers must survive the high-temperature processing of the layers above them, which can exceed 900 °C [1]. "The key tradeoff is that the lower FET tiers must withstand the full thermal budget of the tiers above it," IBM researcher Nirmaan Shankar told the symposium [1]. IBM has previously demonstrated a method for NFETs to endure this process, and at the symposium Shankar detailed a similar advancement for PFETs [1]. The team calculates that extending the process to four tiers of transistors would shrink circuits by 40 percent compared to a two-tiered chip [1]. On the monolithic side, Intel, Samsung, and TSMC are refining their own integration schemes. Intel is using a two-nanosheet structure for each device as a compromise between switching speed and signal-sapping capacitance, though Jami Wiedemer noted this configuration "will likely change as the technology matures" [1]. TSMC has demonstrated CFETs with three different voltage threshold levels for both the top and bottom devices [1]. Samsung reported the first 3-nanosheet PFET and NFET combination [1]. Intel's Myunghee Na called the CFET "the ultimate architecture" but acknowledged the work ahead. "There is still a lot of work cut out for us, but it's a really exciting time," Na said [1]. Commercial introduction of the technology is likely six years away [1].