Records Fall for 3D Chip Tech

Two research teams set new records for a 3D chipmaking technology called hybrid bonding, packing hundreds of thousands more connections per millimeter than previously possible, according to results presented at the IEEE Electronic Components and Technology Conference in Orlando [1]. The advances, from Belgium-based Imec and France's CEA-Leti, drastically reduce bond pitch—the distance between copper connections that bridge stacked chips. Smaller pitches allow more connections in a package, improving computing efficiency [1]. "When we are talking about hybrid bonding at finer pitches, we can directly think about lowering the power consumption, having denser interconnects, and actually improving the communication between devices," said CEA-Leti research engineer Melissa Najem [1]. Hybrid bonding places pads of copper and insulation on the faces of two or more chips, presses them together, and applies heat so the copper expands and joins. The pads must be aligned to within less than a micrometer [1]. Imec, working with equipment maker EV Group, achieved wafer-to-wafer (W2W) pitches of 200 nanometers, down from a previous low of 250 nm announced last year [1]. CEA-Leti's die-to-wafer (D2W) record reached 1 μm, a 50 percent reduction from the last published record of 2 μm, meaning a million connections per square millimeter [1]. W2W bonding requires alignment accuracy down to 50 nm, but the uniformity of silicon wafers eases the task. Imec program director Zsolt Tokei said reaching 200 nm depended on improvements to chemical mechanical polishing, wafer alignment, and copper pad design [1]. Srinidhi Ramamoorthy, an engineer at Applied Materials, noted that some research institutes have fabricated wafers with sub-200 nm W2W pitches but did not publish them alongside electrical testing and reliability data. Without that information, she said, those numbers are "not the final pitch" [1]. For D2W, the 1 μm record hinged more on alignment accuracy than smoothness. Najem said CEA-Leti fine-tuned the alignment process and improved polishing. A test vehicle recorded data for multiple pitch levels; pitches above 1 μm had electrical yields around 90 percent, but that figure dropped to 22 percent for 1 μm [1]. The push for denser chip stacking is driven by the slowing of transistor density gains on single chips. Transistor count, the most common measure of integrated circuit complexity, has historically followed Moore's law, doubling roughly every two years [6]. As those gains become harder to achieve, stacking chips vertically offers an alternative path to higher performance. Huawei, blocked by U.S. export controls from using advanced chipmaking tools, is also pursuing hybrid bonding. The company, founded in Shenzhen in 1987 and now the world's largest telecommunications equipment manufacturer, presented a 1.5 μm hybrid bonding pitch in its coming generation of Kirin processors at the IEEE International Symposium on Circuits and Systems in Shanghai [1][5]. "Connections can be realized in different ways," Imec's Tokei said. "It's never that there is only one way to do things" [1]. Gabriela Pereira, a senior analyst at Yole Group, said mass production pitches remain at 6–9 µm for D2W and 1–2 µm for W2W. Challenges such as alignment and smoothing that complicate research milestones also constrain mass production, which demands speed and replicability [1]. Pereira added that the industry may ultimately favor D2W over W2W because it offers more flexible uses [1]. "A lot of applications are here just waiting for the improvement of die-to-wafer hybrid bonding," Najem said [1].