ReRAM-aware Model Finetuning addressing I-V Non-linearity and Retention Errors

A new finetuning-based training algorithm promises to ease the deployment of deep neural networks on resistive RAM hardware by addressing two key non-idealities without the cost of training from scratch, according to a preprint posted to arXiv on June 16 [1]. Traditional processor architectures are increasingly constrained by the von Neumann bottleneck, which separates memory and computation [2]. In-memory computing using ReRAM crossbar arrays has been proposed as a high-density, energy-efficient alternative, but practical deployment has been held back by hardware imperfections [2]. Existing hardware-aware training methods typically require training models from scratch, a computationally prohibitive step for modern large-scale networks [2]. The new work, submitted to the machine learning section of the open-access repository, introduces a finetuning-based approach that requires minimal training overhead [1]. The algorithm mitigates current-voltage non-linearity by applying a range-shrunk sinh transformation and folds retention errors directly into a regularization loss during finetuning [2]. The authors evaluated the framework on image classification and question-answering tasks [2]. On large-scale models such as ResNet18 and DeiT-Tiny, the method achieved accuracy comparable to the base model [2]. For the MobileNetV3 family tested on the ImageNet dataset, accuracy degradation remained below 2 percent [2]. When applied to the SQuAD v2 question-answering benchmark, the technique resulted in a drop of only 1 point in the F-1 score [2]. arXiv, which began operating in 1991, passed the two-million-article milestone at the end of 2021 and now receives roughly 24,000 submissions per month [6]. The repository hosts preprints that are moderated but not peer-reviewed, spanning fields from physics and mathematics to computer science and quantitative biology [6].